With constant down-scaling and increasingly demanding requirements to the speed, and functionality of advanced Fin Field Effect Transistor (FinFET) technology, there is a growing need for integrated circuits having FinFETs with multiple threshold voltages (Vt) and methods of making the same. This is particularly the case for smaller scale integrated circuits, such as the 14 nanometer (nm) class and beyond.
A typical prior art method of implementing a multiple Vt design for an integrated circuit has been through the implementation of dopants in the channel or fins of the FinFETs. However, such implantation methods lead to high defect density (due to added implanting, etching and the like) and degraded yield.
Another prior art method of making a multiple Vt integrated circuit has been by adjusting the work-function (WF) metal thickness in gates of FinFETs. Typically however, such methods include multiple depositions and removals of WF metal over the high-k dielectric in a gate stack within a FinFET semiconductor region. For example, a first layer of WF metal having a first thickness may be disposed over the high-k dielectrics in the gate stacks of an entire semiconductor region. A first portion of the region may then be masked or blocked off. The first layer of WF metal in a second unmasked portion of the region is then removed by such means as wet etching, dry etching or a suitable combination of both, leaving the dielectric in the second portion exposed again. The mask is then removed from the first portion. A second layer of WF metal having a second thickness is then disposed over the entire region. The result is that the first portion of the semiconductor region has a total WF metal thickness of the combined thicknesses of the first and second WF metal layers, while the second portion of the semiconductor region has a total WF metal thickness of just the second WF metal thickness. Each WF metal thickness will correspond to a different Vt. This process can continue to provide multiple WF metal thicknesses and multiple threshold voltages for multiple portions of a semiconductor region.
Problematically however, such prior art method of adjusting the WF metal requires multiple depositions and removals of the WF metal, which can greatly increase the likelihood of damaging the thin high-k dielectric and WF layers previously formed. Also it increases the possibility of defects in the gate structure due to repeated exposure of the dielectric to etching and other processes.
Accordingly, there is a need for an apparatus and method of implementing a multi-Vt design in an integrated circuit that does not increase the possibility of damaging the channel, fins or gate areas. More specifically, there is a need for an apparatus and method of adjusting the Vt through variations in thicknesses of WF metal in a FinFET integrated circuit that does not involve multiple depositions and removals of the WF metal.